The internalization of storage is spawning another war – this time in memory interconnects. From Anandtech:
This week sees the launch of the Gen-Z Consortium, featuring names such as ARM, Huawei, IBM, Mellanox, Micron, Samsung, SK Hynix and Xilinx, with the purpose of designing a new memory semantic fabric that focuses on the utilization of ‘on-package and storage class memoryʼ (HMC, phase-change, 3D XPoint etc) at the hardware level.
Let’s unpack that.
A bunch of companies, not including Intel or Microsoft, wants to build a standard for using memory as storage. The semantics refer to the limited instruction set that the new bus will use – reads, writes, load, store, put/get – for block-based storage class memory.
Further, they plan to scale the interconnect from nodes – inside the server – to racks.
The consortium has lofty goals:
- Memory media independence. Enable any type and mix of DRAM and non-volatile memory (NVM) to be directly accessed by applications or through block-semantic communications.
- High-bandwidth, low-latency. Efficient, memory-semantic protocol supporting a range of signaling rates and link widths that scale from 10s to 100s of GB/s of bandwidth.
- Multipath. High signaling rates (up to 112 GT/s), and traffic segregation so services and applications may be isolated.
- Scalability. From point-to-point to rack-scale, switch-based topologies.
- Oh, yeah. Cheap too, uses existing form factors and cables.
This all sounds great. But here’s the kicker:
Gen-Z supports a wide variety of component types including processors, memory modules, FPGAs, GPU / GPGPU, DSP, I/O, accelerators, NICs, custom ASICs, and many more.
Processors? And Intel isn’t on board? Micron, of course, is Intel’s partner for 3D XPoint, and, if you look at the ownership of their JV, is in charge. But I think they want to keep Intel happy.
The StorageMojo take
Hurrah for Gen-Z! I like what they’re trying to do, even if the Gen-Z everywhere and anywhere over anything message threatens to fragment the effort into a dozen or more “standard” but incompatible implementations.
Give people a lot of options and they’ll take ’em. Even though they will rarely all choose the same ones.
The larger issue is that the consortium members don’t want to surrender storage class memory to Intel’s tender mercies. And that I support too.
But on-chip interfaces to SCM will be way more performant than off-chip. The Gen-Z Gang of Eight faces an uphill fight, at least in x86 land. OTOH, Intel may face anti-trust scrutiny if they are too aggressive in locking out competing technologies.
I’ll make some popcorn. This will be fun to watch.
Courteous comments welcome, of course.