Spoke to Don Basile and Matt Barletta of Violin Memory Friday. I’ve been talking to Violin for the last couple of years, and while I liked the technology was skeptical of their ability to commercialize it.
That was then.
Today Violin announced a multi-million dollar strategic investment by Toshiba, that gives them runway and access to NAND flash, which is sometimes in short supply thanks to Apple’s success and seasonal demand. They expect to announce more investment and product deals in the next several months.
Don was formerly CEO of Fusion-io. He’s tuned up Violin’s strategy.
Here’s the short version:
- Enterprise focus.
- Move from caching to broad market as a primary storage.
- Aggregation of thousands of NAND chips.
- Interconnect agnostic: FC, FCoE, 10GigE, etc.
- A small, high-performance, energy-efficient storage array.
What they’ve got
They have a unique approach to creating large memory systems:
Violin has developed the industry’s first switched memory architecture. This patent-pending architecture is called Violin Switched Memory (VXM). With VXM, each module is part of a switched array which supports large topologies and fault tolerance while enabling multiple memory types. . . .
Previous memory solutions have not scaled because they relied on classical linear bus topologies. Bus speeds limit the number of registered DIMMs that can be supported in a single channel to fewer than eight and, as speeds increase, to just one or two.
The switches are incorporated into Violin Inline Memory Modules (VIMMs). Data is automatically striped across 5 VIMMs so a VIMM failure does not result in data loss. Failed VIMMs can be replaced without bringing the server down.
Another interesting property of the architecture:
The VXM topology is unique and based on 3 port switches in each of the Violin Intelligent Memory Modules (VIMMs). Each VIMM has a Violin Buffer (VB) device which both implements the 3 port switch and also provides local memory controller functions. The central memory controller provides higher level functions such as the mapping of logical address space to the specific physical VIMMs and memory devices.
The topology . . . allows any two modules within a large network (84 modules) to fail without loss of connectivity to any of the other modules. . . .
In the event of a module failure, the RAID group is rebuilt within a few minutes — much faster than hard disk storage—into any of the global spare modules within the system.
The company claims their array is much faster than an Oracle Exadata 2, and it can run many other apps. They typically see a 6-10x performance improvement from simple insertion along side a standard disk-based array and moving latency critical bits to their box.
Violin’s switched memory architecture aggregates many chips. Because they support large amounts of flash, they can use MLC flash, which is much less expensive, in enterprise applications.
If you had a 100 TB NAND flash array with a 1,000 write cycle spec – typical of 3 or perhaps 4 bit MLC – your system would have to write 100 PB of data to exhaust the array. At a steady 1GB/sec that would take over 3 years.
Go to market
Violin has corralled an impressive list of CIOs for their advisory board. The goal: let them experiment and drive application references.
Primary channel is indirect, but they are pursuing some strategic direct deals to get the ball rolling.
The StorageMojo take
Flash is an architectural game changer for the enterprise. 50 years of disk and array latency mitigation are baked into enterprise thinking. We’re still early in unraveling the interlocking and tacit assumptions that disk issues have imposed on our hardware and application design.
Violin’s clean-sheet design is among the most creative responses to the potential of flash I’ve seen. I wish them luck.
Courteous comments welcome, of course.